1. Technical Field
Embodiments of the invention relate generally to the field of microelectronic devices and more particularly, but not exclusively, to isolation structures for protecting signaling in a substrate.
2. Background Art
System designers are increasingly relying on vertical stacking of integrated circuitry to improve the bandwidth and power requirements for signaling between components. In a typical stacked system, vertical interconnect structures, called through-silicon vias (TSVs), pass through bulk silicon to interconnect integrated circuit chips that are arranged in a stack. By reducing the distance that signals must travel, TSVs often provide for improved bandwidth of communication links. While TSVs typically have low resistance compared to the on-chip wires to which they are connected, the capacitance of a single TSV is often far greater than the capacitance of such on-chip wires. The combination of relatively more resistive on-chip wires and relatively more capacitive TSV can act as a significant RC-based source of signal delay. This delay can limit the maximum bandwidth capacity of a TSV link, and/or may necessitate the use of large transistors for driving signals.
Consequently, TSV capacitance tends to contribute to slower clocking, signal crosstalk coupling and/or other signal integrity complications. As a result, this type of capacitance limits signaling bandwidth capacity of links including TSVs, and/or increases energy requirements for signaling with such links. As successive generations of integrated circuit technologies continue to trend toward smaller scales and faster data rates, the sensitivity of such technology to slew rate characteristics is expected to increase. Accordingly, conventional techniques for mitigating the effects of poor slew rate are expected to be inadequate for the future demands of manufacturers.